MRF39RA Datasheet, PDF (26/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
4.0 DATA PROCESSING
4.1 Overview
4.1.1
BLOCK DIAGRAM
Figure 4-1 illustrates the MRF39RA data processing
circuit. Its role is to interface the data from the
demodulator and the uC access points (SPI and DIO
pins). It also controls all the Configuration registers.
The circuit contains several control blocks that are
described in the following paragraphs.
The MRF39RA implements several data operation
modes, each with their own data path through the data
processing section. Depending on the data operation
mode selected, some control blocks are active while
others remain disabled.
4.1.2
DATA OPERATION MODES
The MRF39RA has two different data operation modes
that the user can select:
• Continuous mode: each received bit is accessed
in real time at the DIO2/DATA pin. This mode may
be used if adequate external signal processing is
available.
• Packet mode (recommended): user only
retrieves payload bytes from the FIFO. The
packet engine automatically removes the
preamble, checks the sync word, performs AES
decryption, checks the CRC and decodes DC-free
schemes, if enabled. The uC processing
overhead is significantly reduced compared to
Continuous mode. Depending on the optional
features activated (CRC, AES, etc) the maximum
payload length is limited to FIFO size, 255 bytes
or unlimited.
Each of these data operation modes is fully described
in the following sections.
FIGURE 4-1:
MRF39RA DATA PROCESSING CONCEPTUAL VIEW
Rx
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR )
D IO0
DIO1
D IO2
D IO3
D IO4
D IO5
SPI
NSS
SCK
MOSI
MISO
Potential datapa ths (data operation mode dependant)
DS40001778B-page 26
 2015 Microchip Technology Inc.