MRF39RA Datasheet, PDF (6/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
2.3.3 PLL ARCHITECTURE
The frequency synthesizer generating the LO
frequency for the receiver is a fractional-N sigma-delta
PLL. The PLL incorporates a third-order loop capable
of fast auto-calibration, and it has a fast switching
time. The VCO and the loop filter are both fully
integrated, removing the need for an external
tight-tolerance, high-Q inductor in the VCO tank circuit.
2.3.3.1 VCO
The VCO runs at two, four or six times the RF
frequency (respectively in the 915, 434 and 315 MHz
bands) to reduce any LO leakage in Receiver mode, to
improve the quadrature precision of the receiver.
The VCO calibration is fully automated. A coarse
adjustment is carried out at Power-on Reset, and a
fine tuning is performed each time the MRF39RA PLL
is activated. Automatic calibration times are fully
transparent to the end user as their processing time is
included in the TS_RE specifications.
2.3.3.2 PLL Bandwidth
The bandwidth of the MRF39RA Fractional-N PLL is
wide enough to enable for very fast PLL lock times,
enabling both short start-up and fast hop times
required for frequency-agile applications.
2.3.3.3 Carrier Frequency and Resolution
The MRF39RA PLL embeds a 19-bit sigma-delta
modulator and its frequency resolution, constant over
the whole frequency range, see Equation 2-1.
EQUATION 2-1: CARRIER FREQUENCY
STEP
F_STEP = ^F----^X-2---^O₁--₉-^S---^C--
The carrier frequency is programmed through RegFrf,
split across addresses 0x07 to 0x09:
EQUATION 2-2: CARRIER FREQUENCY
F_RF = F_STEP  Frf(23,0)
2.3.4 LOCK TIME
PLL lock time TS_FS is a function of a number of
technical factors, such as synthesized frequency,
frequency step, and so on. When using the built-in
sequencer, the MRF39RA optimizes the start-up time
and automatically starts the receiver when the PLL is
locked. To manually control the start-up time, the user
must either wait for TS_FS max as given in the
specification, or monitor the signal PLL lock detect
indicator, which is set when the PLL is within its
locking range.
When performing an AFC, which usually corrects very
small frequency errors, the PLL response time is
shown in Equation 2-3.
EQUATION 2-3: PLL RESPONSE TIME
T_PLLAFC = _P-----_L---_L-5---_B----_W---
In a frequency hopping scheme, the TS_HOP timings
in Table 7-4 give an order of magnitude for the
expected lock times.
2.3.5 LOCK DETECT INDICATOR
A lock indication signal can be made available on
some of the DIO pins, which is toggled high when the
PLL reaches its locking range. Refer to Table 4-2 and
Table 4-3 to map this interrupt to the desired pins.
Note:
The Frf setting is split across three bytes.
A change in the center frequency is only
taken into account when the Least
Significant Byte FrfLsb in RegFrfLsb is
written.
DS40001778B-page 6
 2015 Microchip Technology Inc.