MRF39RA Datasheet, PDF (49/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
5.4 IRQ and Pin Mapping Registers
TABLE 5-4: IRQ AND PIN MAPPING REGISTERS
Name
(Address)
Bits
Variable Name
Mode
Default
Value
Description
RegDioMapping1 7-6 Dio0Mapping
rw
(0x25)
5-4 Dio1Mapping
rw
3-2 Dio2Mapping
rw
1-0 Dio3Mapping
rw
RegDioMapping2 7-6 Dio4Mapping
rw
(0x26)
5-4 Dio5Mapping
rw
3—
r
2-0 ClkOut
rw
RegIrqFlags1
7 ModeReady
r
(0x27)
6 RxReady
r
5—
r
4 PllLock
r
3 Rssi
rwc
2 Timeout
r
1 AutoMode
r
0 SyncAddressMatch r/rwc
00
00
00
00
00
00
0
111*
1
0
0
0
0
0
0
0
Mapping of pins DIO0 to DIO5
See Table 4-2 for mapping in Continuous mode
See Table 4-3 for mapping in Packet mode
Unused
Selects CLKOUT frequency:
000  FXOSC
001  FXOSC/2
010  FXOSC/4
011  FXOSC/8
100  FXOSC/16
101  FXOSC/32
110  RC (automatically enabled)
111  OFF
Set when the operation mode requested in
Mode, is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- Rx: RSSI sampling starts
Cleared when changing operating mode.
Set in Rx mode, after RSSI, AGC and AFC.
Cleared when leaving Rx.
Unused
Set (in FS and Rx) when the PLL is locked.
Cleared when it is not.
Set in Rx when the RssiValue exceeds
RssiThreshold.
Cleared when leaving Rx.
Set when a time-out occurs (see TimeoutRxStart
and TimeoutRssiThresh)
Cleared when leaving Rx or FIFO is emptied.
Set when entering Intermediate mode.
Cleared when exiting Intermediate mode.
Note that in Sleep mode a small delay can be
observed between AutoMode interrupt and the
corresponding Enter/Exit condition.
Set when sync and address (if enabled) are
detected.
Cleared when leaving Rx or FIFO is emptied.
This bit is read-only in Packet mode, rwc in
Continuous mode.
 2015 Microchip Technology Inc.
DS40001778B-page 49