MRF39RA Datasheet, PDF (21/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
3.2.1 RECEIVER START-UP TIME
It is highly recommended to use the built-in sequencer
of the MRF39RA to optimize the delays when setting
the chip in Receive mode. It ensures the shortest start-
up times, hence the lowest possible energy usage for
battery-operated systems.
The start-up times of the receiver can be calculated as
shown in Figure 3-1 through Figure 3-3.
FIGURE 3-1:
Rx START-UP – NO AGC, NO AFC
Rx startup request
(sequencer or user)
TS_RE
XO Started and PLL is locked
ModeReady
RxReady
Analog FE’s
group delay
Tana
Channel Filter’s
group delay
Tcf
DC Cutoff’s RSSI
RSSI
group delay sampling sampling
Tdcc
Trssi
Trssi
Reception of Packet
Received Packet Preamble may start
FIGURE 3-2:
Rx START-UP – AGC, NO AFC
Rx startup request
(sequencer or user)
TS_RE_AGC
The LNA gain is adjusted by
the AGC, according to the
RSSI result
XO Started and PLL is locked
ModeReady
Analog FE’s
group delay
Tana
Channel Filter’s
group delay
Tcf
DC Cutoff’s RSSI
RSSI
group delay sampling sampling
Tdcc
Trssi
Trssi
Channel Filter’s
group delay
Tcf
DC Cutoff’s RSSI
group delay sampling
Tdcc
Trssi
Reception of Packet
RxReady
Received Packet Preamble may start
FIGURE 3-3:
Rx START-UP – AGC AND AFC
Rx startup request
(sequencer or user)
TS_RE_AGC&AFC
The LNA gain is adjusted by
the AGC, according to the
RSSI result
Carrier Frequency is adjusted
by the AFC
XO Started and Analog FE’s Channel Filter’s DC Cutoff’s RSSI
RSSI Channel Filter’s DC Cutoff’s RSSI
PLL is locked group delay group delay group delay sampling sampling group delay group delay sampling
AFC
PLL
lock
Channel Filter’s
group delay
DC Cutoff’s
group delay
Reception of Packet
Tana
Tcf
Tdcc
Trssi
Trssi
Tcf
Tdcc
Trssi Tafc Tpllafc
Tcf
ModeReady
Tdcc
RxReady
Received Packet Preamble may start
The different timings shown above are as follows:
• Group delay of the analog front end: Tana = 20 µs
• Channel filter’s group delay in FSK mode:
Tcf = 21/(4.RxBw)
• Channel filter’s group delay in OOK mode:
Tcf = 34/(4.RxBw)
• DC Cutoff’s group delay: Tdcc = max(8,
2^(round(log2(8.RxBw.Tbit)+1))/(4.RxBw)
• PLL lock time after AFC adjustment: Tpllafc = 5/
PLLBW (PLLBW = 300 kHz)
• AFC sample time: Tafc = 4 x Tbit (also denoted
TS_AFC in the general specification)
• RSSI sample time: Trssi = 2 x int(4.RxBw.Tbit)/
(4.RxBw) (also known as TS_RSSI).
Note:
The timings represent maximum settling
times. Shorter settling times may be
observed in real cases.
 2015 Microchip Technology Inc.
DS40001778B-page 21