MRF39RA Datasheet, PDF (29/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
4.2.2.4 FIFO Clearing
Table 4-1 summarizes the status of the FIFO when
switching between different modes.
TABLE 4-1: STATUS OF FIFO WHEN SWITCHING BETWEEN DIFFERENT MODES
From
To
FIFO status
Comments
Stdby
Sleep
Stdby/Sleep
Rx
Sleep
Stdby
Rx
Stdby/Sleep
Not cleared
Not cleared
Cleared
Not cleared
To enable the user to read FIFO in Stdby/Sleep mode after Rx
4.2.3 SYNC WORD RECOGNITION
4.2.3.1 Overview
Sync word recognition, also called pattern recognition,
is activated by setting SyncOn in RegSyncConfig. The
bit synchronizer must also be activated in Continuous
mode (automatically done in Packet mode).
The block behaves like a Shift register; it continuously
compares the incoming data with its internally
programmed sync word and sets SyncAddressMatch
when a match is detected as illustrated in Figure 4-5.
FIGURE 4-5:
SYNC WORD RECOGNITION
Rx DATA
(NRZ)
Bit N-x =
Sync_value[x]
Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
DCLK
SyncAddressMatch
During the comparison of the demodulated data, the
first bit received is compared with bit 7 (MSB) of
RegSyncValue1 and the last bit received is compared
with bit 0 (LSB) of the last byte whose address is
determined by the length of the sync word.
When the programmed sync word is detected, the user
can assume that this incoming packet is for the node
and can be processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO
is emptied.
4.2.3.2 Configuration
• Size: sync word size is set from 1 to 8 bytes (i.e.,
8 to 64 bits) via SyncSize in RegSyncConfig
• Error tolerance: the number of errors tolerated in
the sync word recognition is set from 0 to 7 bits
via SyncTol
• Value: the sync word value is configured in
SyncValue(63:0)
Note: SyncValue choices containing 0x00 bytes
are not allowed.
4.2.4 PACKET HANDLER
The packet handler is the block used in Packet mode.
Its functionality is fully described in Section 4.5
“Packet Mode”.
4.2.5 CONTROL
The control block configures and controls the full chip
behavior according to the settings programmed in the
Configuration registers.
 2015 Microchip Technology Inc.
DS40001778B-page 29