MRF39RA Datasheet, PDF (37/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

4.5.3 PROCESSING (WITHOUT AES)
In Rx mode the packet handler extracts the user
payload to the FIFO by performing the following
operations:
• Receiving the preamble and stripping it off
• Detecting the sync word and stripping it off
• Optional DC-free decoding of data
• Optionally checking the address byte
• Optionally checking CRC and reflecting the result
on CrcOk.
Only the payload (including optional address and
length fields) is made available in the FIFO.
When the Rx mode is enabled the demodulator
receives the preamble followed by the detection of sync
word. If fixed length packet format is enabled, then the
number of bytes received as the payload is given by the
PayloadLength parameter.
In Variable Length mode, the first byte received after
the sync word is interpreted as the length of the
received packet. The internal length counter is
initialized to this received length. The PayloadLength
register is set to a value which is greater than the
maximum expected length of the received packet. If the
received length is greater than the maximum length
stored in PayloadLength register, the packet is
discarded; otherwise, the complete packet is received.
If the address check is enabled, then the second byte
received in case of variable length and first byte in case
of fixed length is the address byte. If the address
matches the one in the NodeAddress field, reception of
the data continues; otherwise, it is stopped. The CRC
check is performed if CrcOn = 1 and the result is
available in CrcOk, indicating that the CRC was
successful. An interrupt (PayloadReady) is also
generated on DIO0 as soon as the payload is available
in the FIFO. The payload available in the FIFO can also
be read in Sleep/Standby mode.
If the CRC fails, the PayloadReady interrupt is not
generated and the FIFO is cleared. This function is
overridden by setting CrcAutoClearOff = 1, thus forcing
the availability of the PayloadReady interrupt and the
payload in the FIFO, even if the CRC fails.
MRF39RA
4.5.4 AES
AES is the symmetric-key block cipher that provides
the cryptographic capabilities to the receiver. The
system proposed can work with 128-bit long fixed keys.
The fixed key is stored in a 16-byte write-only user
Configuration register, which retains its value in Sleep
mode.
As shown in Figure 4-9 and Figure 4-10, the message
part of the packet can be decrypted with the 128-cipher
key stored in the Configuration registers.
4.5.4.1 Processing
The data received is stored in the FIFO. The address,
CRC interrupts are generated as usual because these
parameters were not encrypted.
As soon as the complete packet is received, the data is
read from the FIFO, decrypted, and written back to
FIFO. The PayloadReady interrupt is issued once the
decrypted data is ready for reading in the FIFO via the
SPI interface.
The AES decryption cannot be used on the fly (i.e.,
while receiving data). Thus, when AES decryption is
enabled, the FIFO acts as a simple buffer. The
decryption is only initiated when the complete packet is
received in the buffer.
The decryption process takes approximately 7.0 µs per
16-byte block. For a maximum of four blocks (i.e., 64
bytes) it can take up to 28 µs for completing the
cryptographic operations.
The receiver sees the AES decryption time as a
sequential delay before the PayloadReady interrupt is
available.
In Fixed Length mode, the message part of the payload
that can be decrypted is 64-byte long. If the address
filtering is enabled, the length of the payload must be at
maximum 65 bytes in this case.
In Variable Length mode the maximum message size
that can be decrypted is also 64 bytes whether address
comparison is enabled or not. Thus, including length
byte, the length of the payload is either 65 or 66 bytes
maximum (the latter, when address comparison is
enabled).
Crc check being performed on encrypted data, CrcOk
interrupt occurs “decryption time” before
PayloadReady interrupt.
 2015 Microchip Technology Inc.
DS40001778B-page 37