MRF39RA Datasheet, PDF (50/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
TABLE 5-4: IRQ AND PIN MAPPING REGISTERS (CONTINUED)
Name
(Address)
Bits
Variable Name
Mode
Default
Value
Description
RegIrqFlags2
(0x28)
RegRssiThresh
(0x29)
RegRxTimeout1
(0x2A)
RegRxTimeout2
(0x2B)
7 FifoFull
r
6 FifoNotEmpty
r
5 FifoLevel
r
4 FifoOverrun
rwc
3—
r
2 PayloadReady
r
1 CrcOk
r
0 LowBat
rwc
7-0 RssiThreshold
rw
7-0 TimeoutRxStart
rw
7-0 TimeoutRssiThresh rw
0
0
0
0
0
0
0
—
0xE4*
0x00
0x00
Set when FIFO is full (i.e., contains 66 bytes),
else cleared.
Set when FIFO contains at least one byte, else
cleared
Set when the number of bytes in the FIFO
strictly exceeds FifoThreshold, else cleared.
Set when FIFO overrun occurs. (except in Sleep
mode)
Flag(s) and FIFO are cleared when this bit is
set. The FIFO then becomes immediately
available for the next reception.
Unused
Set in Rx when the payload is ready (i.e., last
byte received and CRC is OK if enabled and
CrcAutoClearOff is cleared). Cleared when
FIFO is empty.
Set in Rx when the CRC of the payload is OK.
Cleared when FIFO is empty.
Set when the battery voltage drops below the
low battery threshold. Only cleared when set by
the user.
RSSI trigger level for Rssi interrupt:
- RssiThreshold / 2 [dBm]
Time-out interrupt is generated
TimeoutRxStart*16*T_bit after switching to Rx
mode if Rssi interrupt does not occur (i.e.,
RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
Time-out interrupt is generated
TimeoutRssiThresh*16*T_bit after Rssi interrupt if
PayloadReady interrupt does not occur.
0x00: TimeoutRssiThresh is disabled
DS40001778B-page 50
 2015 Microchip Technology Inc.