MRF39RA Datasheet, PDF (28/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
4.2.2 FIFO
4.2.2.1 Overview and Shift Register (SR)
In Packet mode of operation, received data is stored in
a configurable FIFO (First In First Out) device. It is
accessed via the SPI interface and provides several
interrupts for transfer management.
The FIFO is 1-byte wide, hence it only performs byte
(parallel) operations, whereas the demodulator
functions serially. A Shift register is therefore employed
to interface the two devices. In Rx the Shift register gets
bit by bit data from the demodulator and writes these
byte by byte to the FIFO as illustrated in Figure 4-3.
FIGURE 4-3:
FIFO AND SHIFT
REGISTER (SR)
Rx Data
1
MSB
byte1
byte0
8
SR (8bits)
FIFO
LSB
4.2.2.2 Size
The FIFO size is fixed to 66 bytes.
4.2.2.3 Interrupt Sources and Flags
• FifoNotEmpty: FifoNotEmpty interrupt source is
low when byte 0 (i.e., whole FIFO, is empty).
Otherwise it is high. Note that when retrieving
data from the FIFO, FifoNotEmpty is updated on
NSS falling edge (i.e., when FifoNotEmpty is
updated to low state, the currently started read
operation must be completed). In other words,
FifoNotEmpty state must be checked after each
read operation for a decision on the next one
(FifoNotEmpty = 1: more bytes to read;
FifoNotEmpty = 0: no more bytes to read).
• FifoFull: Fifofull interrupt source is high when the
last FIFO byte (i.e., the whole FIFO, is full).
Otherwise, it is low.
• FifoOverrunFlag: FifoOverrunFlag is set when a
new byte is written by the SR while the FIFO is
already full. Data is lost and the flag must be
cleared by writing a ‘1’, note that the FIFO is also
be cleared.
• FifoLevel: Threshold is programmed by
FifoThreshold in RegFifoThresh. Its behavior is
illustrated in Figure 4-4.
Note:
When switching to Sleep mode, only use
the FIFO once the ModeReady flag is set
(quasi immediate from all modes).
FIGURE 4-4:
FIFOLEVEL IRQ SOURCE BEHAVIOR
FifoLevel
1
0
DS40001778B-page 28
B B+1
# of bytes in FIFO
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