MRF39RA Datasheet, PDF (10/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
2.4.3 CONTINUOUS-TIME DAGC
In addition to the automatic gain control described in
Section 2.4.2 “Automatic Gain Control”, the
MRF39RA is capable of continuously adjusting its gain
in the digital domain, after the Analog-to-Digital
conversion has occurred. This feature, named DAGC,
is fully transparent to the end user. The digital gain
adjustment is repeated every two bits and has the
following benefits:
• Fully transparent to the end user
• Improves the fading margin of the receiver during
the reception of a packet, even if the gain of the
LNA is frozen
• Improves the receiver robustness in fast fading
signal conditions by quickly adjusting the receiver
gain (every two bits)
• Works in Continuous, Packet and Unlimited
Length Packet modes.
The DAGC is enabled by setting RegTestDagc to 0x20
for low modulation index systems (i.e., when
AfcLowBetaOn = ‘1’) and 0x30 for other systems. See
Section 2.4.17 “Optimized Setup for Low
Modulation Index Systems”. It is recommended to
always enable the DAGC.
2.4.4
QUADRATURE MIXER – ADCs –
DECIMATORS
The mixer is inserted between the output of the RF
buffer stage and the input of the Analog-to-Digital
Converter (ADC) of the receiver section. This block is
designed to translate the spectrum of the input RF
signal to base-band, and offer both high IIP2 and IIP3
responses.
In the lower bands of operation (290 to 510 MHz), the
multi-phase mixing architecture with weighted phases
improves the rejection of the LO harmonics in
Receiver mode, hence increasing the receiver
immunity to out-of-band interferers.
The I and Q digitalization is made by two 5th order
continuous-time sigma-delta Analog-to-Digital
Converters (ADC). Gain is not constant over
temperature, but the whole receiver is calibrated
before reception that this inaccuracy has no impact on
the RSSI precision. The ADC output is one bit per
channel. It needs to be decimated and filtered
afterwards. This ADC can also be used for
temperature measurement. For more details, refer to
Section 2.4.18 “Temperature Sensor”.
The decimators decrease the sample rate of the
incoming signal to optimize the area and power
consumption of the following receiver blocks.
2.4.5 CHANNEL FILTER
The role of the channel filter is to filter out the noise and
interferers outside of the channel. Channel filtering on
the MRF39RA is implemented with a 16-tap finite
impulse response (FIR) filter, providing an outstanding
adjacent channel rejection performance, even for
narrow-band applications.
Note:
To respect oversampling rules in the
decimation chain of the receiver, the bit
rate cannot be set at a higher value than
two times the single-side receiver
bandwidth (BitRate < 2 x RxBw)
The single-side channel filter bandwidth RxBw is
controlled by the RxBwMant and RxBwExp parameters
in RegRxBw, as shown in Equation 2-5.
EQUATION 2-5: RXBW
When FSK modulation is enabled:
RxBw = _{R-----x---B----w----M-----a---F-n---Xt---}-O----2-S--_R-C--_x---_B---_w----_E---_x--_p----₊----₂-
When OOK modulation is enabled:
RxBw
=
------------------------F----X----O-----S---C--------------------------
RxBwMant  2^{RxBwExp + 3}
DS40001778B-page 10
 2015 Microchip Technology Inc.