MRF39RA Datasheet, PDF (32/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
4.4 Continuous Mode
4.4.1 GENERAL DESCRIPTION
As illustrated in Figure 4-6, in Continuous mode, the
NRZ data from the demodulator is directly accessed by
the uC on the DIO2/DATA pin. The FIFO and packet
handler are inactive.
FIGURE 4-6:
CONTINUOUS MODE CONCEPTUAL VIEW
Rx
CONTROL
Data
Rx _SYNC
RECOG.
SPI
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
NSS
SCK
MOSI
MISO
4.4.2 RX PROCESSING
If the bit synchronizer is disabled, the raw demodulator
output is made directly available on DATA pin and no
DCLK signal is provided.
Conversely, if the bit synchronizer is enabled,
synchronous cleaned data and clock are made
available on DIO2/DATA and DIO1/DCLK pins,
respectively. DATA is sampled on the rising edge of
DCLK and updated on the falling edge as illustrated in
Figure 4-7.
FIGURE 4-7:
RX PROCESSING IN CONTINUOUS MODE
DATA (NRZ)
DCLK
Note:
In Continuous mode it is always
recommended to enable the bit
synchronizer to clean the DATA signal
even if the DCLK signal is not used by the
uC (bit synchronizer is automatically
enabled in Packet mode).
DS40001778B-page 32
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