MRF39RA Datasheet, PDF (27/72 Pages) Microchip Technology – Low-Power, Integrated UHF Receiver

MRF39RA
4.2 Control Block Description
4.2.1 SPI INTERFACE
The SPI interface gives access to the Configuration
register via a synchronous full-duplex protocol
corresponding to CPOL = 0 and CPHA = 0 in Motorola/
Freescale nomenclature. Only the slave side is
implemented.
Three access modes to the registers are provided:
• Single Access: an address byte followed by a
data byte is sent for a write access, whereas an
address byte is sent and a read byte is received
for the read access. The NSS pin goes low at the
beginning of the frame and goes high after the
data byte.
• Burst Access: the address byte is followed by
several data bytes. The address is automatically
incremented internally between each data byte.
This mode is available for both read and write
accesses. The NSS pin goes low at the beginning
of the frame and stays low between each byte. It
goes high only after the last byte transfer.
• FIFO access: if the address byte corresponds to
the address of the FIFO, then succeeding data
byte contains the address of the FIFO. The
address is not automatically incremented, but it is
memorized and does not need to be sent between
each data byte. The NSS pin goes low at the
beginning of the frame and stays low between
each byte. It goes high only after the last byte
transfer.
Figure 4-2 shows a typical SPI single access to a
register.
MOSI is generated by the master on the falling edge of
SCK and is sampled by the slave (i.e., this SPI
interface) on the rising edge of SCK. MISO is
generated by the slave on the falling edge of SCK.
A transfer always starts by the NSS pin going low.
MISO is high-impedance when NSS is high.
The first byte is the address byte. It is made of:
• wnr bit, which is ‘1’ for write access and ‘0’ for
read access
• 7 bits of address, MSB first
The second byte is a data byte, either sent on MOSI by
the master in case of a write access, or received by the
master on MISO in case of a read access. The data
byte is transmitted MSB first.
Proceeding bytes may be sent on MOSI (for write
access) or received on MISO (for read access) without
rising NSS and re-sending the address. In FIFO mode,
if the address was the FIFO address, then the bytes will
is read at the FIFO address. In Burst mode, if the
address was not the FIFO address, then it is
automatically incremented at each new byte received.
The frame ends when NSS goes high. The next frame
must start with an address byte. The Single Access
mode is actually a special case of FIFO/Burst mode
with only one data byte transferred.
During the write access, the byte transferred from the
slave to the master on the MISO line is the value of the
written register before the write operation.
FIGURE 4-2:
SPI TIMING DIAGRAM (SINGLE ACCESS)
 2015 Microchip Technology Inc.
DS40001778B-page 27