PIC32MX1XX Datasheet, PDF(44/320 Page) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

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PIC32MX1XX Datasheet, PDF (44/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

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TABLE 4-2: INTERRUPT REGISTER MAP(1) (CONTINUED)

Bits

31/15 30/14 29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2 17/1 16/0

31:16 â

â

â

1110 IPC8

15:0 â

â

â

PMPIP<2:0>

I2C1IP<2:0>

PMPIS<1:0>

I2C1IS<1:0>

â

â

â

â

â

â

CNIP<2:0>

U1IP<2:0>

CNIS<1:0>

U1IS<1:0>

0000

0000

31:16 â

â

â

1120 IPC9

15:0 â

â

â

CTMUIP<2:0>

U2IP<2:0>

CTMUIS<1:0>

â

â

â

U2IS<1:0>

â

â

â

I2C2IP<2:0>

SPI2IP<2:0>

I2C2IS<1:0>

SPI2IS<1:0>

0000

0000

31:16 â

â

â

1130 IPC10

15:0 â

â

â

DMA3IP<2:0>

DMA1IP<2:0>

DMA3IS<1:0>

â

â

â

DMA1IS<1:0>

â

â

â

DMA2IP<2:0>

DMA0IP<2:0>

DMA2IS<1:0>

DMA0IS<1:0>

0000

0000

Legend: x = unknown value on Reset; â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Note 1:

2:

3:

With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 âCLR,

SET and INV Registersâ for more information.

These bits are not available on PIC32MX1XX devices.

This register does not have associated CLR, SET, INV registers.

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