PIC32MX1XX Datasheet, PDF (186/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31:24
23:16
15:8
7:0
U-0
U-0
—
—
U-0
U-0
—
—
R/W-0
U-0
ON⁽¹⁾
—
R/W-0
R/W-0
CSF<1:0>⁽²⁾
U-0
—
U-0
—
R/W-0
SIDL
R/W-0
ALP⁽²⁾
U-0
U-0
—
—
U-0
U-0
—
—
R/W-0
R/W-0
ADRMUX<1:0>
U-0
R/W-0
—
CS1P⁽²⁾
U-0
—
U-0
—
R/W-0
PMPTTL
U-0
—
Bit
25/17/9/1
U-0
—
U-0
—
R/W-0
PTWREN
R/W-0
WRSP
Bit
24/16/8/0
U-0
—
U-0
—
R/W-0
PTRDEN
R/W-0
RDSP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Parallel Master Port Enable bit⁽¹⁾
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and
PMA<14>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
bit 7-6
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF<1:0>: Chip Select Function bits⁽²⁾
11 = Reserved
10 = PMCS1 function as Chip Select
01 = PMCS1 functions as address bit 14
00 = PMCS1 function as address bit 14
bit 5
ALP: Address Latch Polarity bit⁽²⁾
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS61168D-page 186
Preliminary
© 2011-2012 Microchip Technology Inc.