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PIC32MX1XX Datasheet, PDF (135/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog
PIC32MX1XX/2XX
REGISTER 10-11: U1CON: USB CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
R-x
JSTATE
U-0
—
U-0
—
U-0
—
R-x
SE0
U-0
—
U-0
—
U-0
—
R/W-0
PKTDIS(4)
TOKBUSY(1,5)
U-0
—
U-0
—
U-0
—
R/W-0
USBRST
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
HOSTEN(2) RESUME(3)
U-0
—
U-0
—
U-0
—
R/W-0
PPBRST
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
R/W-0
USBEN(4)
SOFEN(5)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE detected on the USB
0 = No JSTATE detected
bit 6 SE0: Live Single-Ended Zero flag bit
1 = Single Ended Zero detected on the USB
0 = No Single Ended Zero detected
bit 5 PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token being executed by the USB module
0 = No token being executed
bit 4 USBRST: Module Reset bit(5)
1 = USB reset generated
0 = USB reset terminated
bit 3 HOSTEN: Host Mode Enable bit(2)
1 = USB host capability enabled
0 = USB host capability disabled
bit 2 RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling activated
0 = RESUME signaling disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 10-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the
RESUME signaling when this bit is cleared.
Device mode.
Host mode.
© 2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 135