PIC32MX1XX Datasheet, PDF (194/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 20-1: RTCCON: RTC CONTROL REGISTER⁽¹⁾
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
U-0
—
R/W-0
U-0
—
R/W-0
15:8
7:0
R/W-0
U-0
ON^(2,3)
—
R/W-0
R-0
RTSECSEL⁽⁴⁾ RTCCLKON
U-0
—
R/W-0
R/W-0
SIDL
U-0
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
CAL<9:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL<7:0>
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
R/W-0
R-0
R-0
R/W-0
—
RTCWREN⁽⁵⁾ RTCSYNC HALFSEC⁽⁶⁾ RTCOE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
bit 15
•
•
•
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute
ON: RTCC On bit^(2,3)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7
RTSECSEL: RTCC Seconds Clock Output Select bit⁽⁴⁾
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
bit 6
RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
6:
This register is reset only on a Power-on Reset (POR).
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
DS61168D-page 194
Preliminary
© 2011-2012 Microchip Technology Inc.