PIC32MX1XX Datasheet, PDF (196/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 20-2: RTCALRM: RTC ALARM CONTROL REGISTER⁽¹⁾
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
31:24
23:16
15:8
7:0
U-0
—
U-0
—
R/W-0
ALRMEN^(2,3)
R/W-0
U-0
—
U-0
—
R/W-0
CHIME⁽³⁾
R/W-0
U-0
—
U-0
—
R/W-0
PIV⁽³⁾
R/W-0
U-0
U-0
—
—
U-0
U-0
—
—
R-0
ALRMSYNC⁽⁴⁾
R/W-0
R/W-0
R/W-0
ARPT<7:0>⁽³⁾
U-0
U-0
—
—
U-0
U-0
—
—
R/W-0
R/W-0
AMASK<3:0>⁽³⁾
R/W-0
R/W-0
Bit
24/16/8/0
U-0
—
U-0
—
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ALRMEN: Alarm Enable bit^(2,3)
bit 14
1 = Alarm is enabled
0 = Alarm is disabled
CHIME: Chime Enable bit⁽³⁾
bit 13
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
PIV: Alarm Pulse Initial Value bit⁽³⁾
bit 12
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
ALRMSYNC: Alarm Sync bit⁽⁴⁾
bit 11-8
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
clocks away from a half-second rollover
AMASK<3:0>: Alarm Mask Configuration bits⁽³⁾
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved; do not use
1011 = Reserved; do not use
11xx = Reserved; do not use
Note 1:
2:
3:
4:
This register is reset only on a Power-on Reset (POR).
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
DS61168D-page 196
Preliminary
© 2011-2012 Microchip Technology Inc.