PIC32MX1XX Datasheet, PDF (165/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral Interface (SPI)” (DS61106) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters (ADC), etc.
The PIC32 SPI module is compatible with Motorola^®
SPI and SIOP interfaces.
Some of the key features of the SPI module are:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data width
• Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during CPU Sleep and Idle mode
• Audio Codec Support:
- I²S protocol
- Left-justified
- Right-justified
- PCM
FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
Read
SPIxBUF
Write
SPIxRXB FIFO SPIxTXB FIFO
FIFOs Share Address SPIxBUF
Transmit
SDIx
Receive
SPIxSR
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
Edge
Select
SCKx
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
MCLKSEL
Baud Rate
Generator
MSTEN
REFCLK
PBCLK
© 2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 165