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PIC32MX1XX Datasheet, PDF (158/320 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog | |||
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PIC32MX1XX/2XX
REGISTER 13-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(2)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
bit 2
Unimplemented: Read as â0â
bit 1
TCS: Timer Clock Source Select bit(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as â0â
Note 1:
2:
3:
4:
When using 1:1 PBCLK divisor, the userâs software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the moduleâs ON bit.
This bit is available only on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and
Timer5). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
DS61168D-page 158
Preliminary
© 2011-2012 Microchip Technology Inc.
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