PIC24FJ256GA110_10 Datasheet, PDF (4/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
Special Microcontroller Features:
• Operating Voltage Range of 2.0V to 3.6V
• Self-Reprogrammable under Software Control
• 5.5V Tolerant Input (digital pins only)
• Configurable Open-Drain Outputs on Digital I/O
• High-Current Sink/Source (18 mA/18 mA) on all I/O
• Selectable Power Management modes:
- Sleep, Idle and Doze modes with fast wake-up
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip
FRC oscillator
• On-Chip LDO Regulator
Pin Diagram (64-Pin TQFP and QFN⁽¹⁾)
• Power-on Reset (POR), Power-up Timer (PWRT),
Low-Voltage Detect (LVD) and Oscillator Start-up Timer
(OST)
• Flexible Watchdog Timer (WDT) with On-Chip
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
• JTAG Boundary Scan Support
• Brown-out Reset (BOR)
• Flash Program Memory:
- 10,000 erase/write cycle endurance (minimum)
- 20-year data retention minimum
- Selectable write protection boundary
- Write protection option for Flash Configuration
Words
CN63/PMD5/RE5
1
SCL3/CN64/PMD6/RE6
2
SDA3/CN65/PMD7/RE7
3
PMA5/RP21/C1IND/CN8/RG6
4
C1INC/RP26/CN9/PMA4/RG7
5
C2IND/RP19/CN10/PMA3/RG8
6
MCLR
7
C2INC/RP27/CN11/PMA2/RG9
8
VSS
9
VDD
10
PGEC3/AN5/C1INA/RP18/CN7/RB5
11
PGED3/AN4/C1INB/RP28/CN6/RB4
12
AN3/C2INA/CN5/RB3
13
AN2/C2INB/RP13/CN4/RB2
14
PGEC1/AN1/VREF-/RP1/CN3/RB1
15
PGED1/AN0/VREF+/RP0/CN2/PMA6/RB0
16
PIC24FJ64GA106
PIC24FJ128GA106
PIC24FJ192GA106
PIC24FJ256GA106
48
SOSCO/C3INC/RPI37/T1CK/CN0/RC14
47
SOSCI/C3IND/CN1/RC13
46
RP11/CN49/RD0
45
RP12/CN56/PMCS1/RD11
44
RP3/CN55/PMCS2/RD10
43
RP4/CN54/RD9
42
RTCC/RP2/CN53/RD8
41
VSS
40
OSCO/CLKO/CN22/RC15
39
OSCI/CLKI/CN23/RC12
38
VDD
37
SCL1/CN83/RG2
36
SDA1/CN84/RG3
35
ASCK1/RPI45/INT0/CN72/RF6
34
RP30/CN70/RF2
33
RP16/CN71/RF3
Legend:
Note 1:
Shaded pins indicate pins tolerant to up to +5.5 VDC.
RPn represents remappable pins for Peripheral Pin Select (PPS) feature.
For QFN devices, the backplane on the underside of the device must also be connected to VSS.
DS39905E-page 4
 2010 Microchip Technology Inc.