PIC24FJ256GA110_10 Datasheet, PDF (10/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
1.2 Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ256GA110 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are three independent I²C™
modules that support both Master and Slave
modes of operation. Devices also have, through
the Peripheral Pin Select (PPS) feature, four
independent UARTs with built-in IrDA^®
encoder/decoders and three SPI modules.
• Analog Features: All members of the
PIC24FJ256GA110 family include a 10-bit A/D
Converter module and a triple comparator
module. The A/D module incorporates program-
mable acquisition time, allowing for a channel to
be selected and a conversion to be initiated with-
out waiting for a sampling period, as well as faster
sampling speeds. The comparator module
includes three analog comparators that are
configurable for a wide range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ256GA110
family include the brand new CTMU interface
module. This provides a convenient method for
precision time measurement and pulse genera-
tion, and can serve as an interface for capacitive
sensors.
• Parallel Master Port: One of the general purpose
I/O ports can be reconfigured for enhanced
parallel data communications. In this mode, the
port can be configured for both master and slave
operations, and supports 8-bit transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up the timer
resources and program memory space for the use
of the core application.
1.3 Details on Individual Family
Members
Devices in the PIC24FJ256GA110 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in four
ways:
1. Flash program memory (64 Kbytes for
PIC24FJ64GA1 devices, 128 Kbytes for
PIC24FJ128GA1 devices, 192 Kbytes for
PIC24FJ192GA1 devices and 256 Kbytes for
PIC24FJ256GA1 devices).
2. Available I/O pins and ports (53 pins on 6 ports
for 64-pin devices, 69 pins on 7 ports for 80-pin
devices and 85 pins on 7 ports for 100-pin
devices).
3. Available Interrupt-on-Change Notification (ICN)
inputs (same as the number of available I/O pins
for all devices).
4. Available remappable pins (31 pins on 64-pin
devices, 42 pins on 80-pin devices and 46 pins
on 100-pin devices)
All other features for devices in this family are identical.
These are summarized in Table 1-1.
A list of the pin features available on the
PIC24FJ256GA110 family devices, sorted by function,
is shown in Table 1-4. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
this data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
DS39905E-page 10
 2010 Microchip Technology Inc.