PIC24FJ256GA110_10 Datasheet, PDF (130/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
10.4.2 AVAILABLE PERIPHERALS
The peripherals managed by the Peripheral Pin Select
are all digital only peripherals. These include general
serial communications (UART and SPI), general purpose
timer clock inputs, timer related peripherals (input
capture and output compare) and external interrupt
inputs. Also included are the outputs of the comparator
module, since these are discrete digital signals.
Peripheral Pin Select is not available for I²C™, change
notification inputs, RTCC alarm outputs or peripherals
with analog inputs.
A key difference between pin select and non pin select
peripherals is that pin select peripherals are not asso-
ciated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
10.4.2.1 Peripheral Pin Select Function
Priority
Pin-selectable peripheral outputs (e.g. OC, UART
Transmit) take priority over general purpose digital
functions on a pin, such as PMP and port I/O. Special-
ized digital outputs, such as USB functionality, will take
priority over PPS outputs on the same pin. The pin
diagrams provided at the beginning of this data sheet
list peripheral outputs in order of priority. Refer to them
for priority concerns on a particular pin.
Unlike PIC24F devices with fixed peripherals,
pin-selectable peripheral inputs never take ownership
of a pin. The pin’s output buffer is controlled by the
TRISx setting or by a fixed peripheral on the pin. If the
pin is configured in Digital mode, the PPS input will
operate correctly. If an analog function is enabled on
the pin, the PPS input will be disabled.
10.4.3
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
The association of a peripheral to a
peripheral-selectable pin is handled in two different
ways, depending on if an input or an output is being
mapped.
10.4.3.1 Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-21). Each register contains two
sets of 6-bit fields, with each set associated with one of
the pin-selectable peripherals. Programming a given
peripheral’s bit field with an appropriate 6-bit value
maps the RPn pin with that value to that peripheral. For
any given device, the valid range of values for any of
the bit fields corresponds to the maximum number of
Peripheral Pin Select options supported by the device.
10.4.3.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains two 6-bit fields, with each field
being associated with one RPn pin (see Register 10-22
through Register 10-37). The value of the bit field cor-
responds to one of the peripherals and that peripheral’s
output is mapped to the pin (see Table 10-3).
Because of the mapping technique, the list of peripher-
als for output mapping also includes a null value of
‘000000’. This permits any given pin to remain
disconnected from the output of any of the pin-selectable
peripherals.
10.4.3.3 Alternate Fixed Pin Mapping
To provide a migration option from earlier high pin count
PIC24F devices, PIC24FJ256GA110 family devices
implement an additional option for mapping the clock
output (SCK) of SPI1. This option permits users to map
SCK1OUT specifically to the fixed pin function, ASCK1.
The SCK1CM bit (ALTRP<0>) controls this mapping;
setting the bit maps SCK1OUT to ASCK1.
The SCK1CM bit must be set (= 1) before enabling the
SPI module. It must remain set while transactions using
SPI1 are in progress, in order to prevent transmission
errors; when the module is disabled, the bit must be
cleared. Additionally, no other RPOUT register should
be configured to output the SCK1OUT function while
SCK1CM is set.
DS39905E-page 130
 2010 Microchip Technology Inc.