PIC24FJ256GA110_10 Datasheet, PDF (297/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
FIGURE 28-18:
I²C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM11
IM21
SCLx
SDAx
In
IM20
IM10
SDAx
Out
Note: Refer to Figure 28-4 for load conditions.
IM26
IM25
IM40
IM45
TABLE 28-31: I²C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C (Industrial)
Param
No.
Symbol
Characteristic
Min⁽¹⁾
Max Units
Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
—
s
—
400 kHz mode TCY/2 (BRG + 1) —
s
—
1 MHz mode⁽²⁾ TCY/2 (BRG + 1)
—
s
—
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
s
—
400 kHz mode TCY/2 (BRG + 1) —
s
—
1 MHz mode⁽²⁾ TCY/2 (BRG + 1)
—
s
—
IM20 TF:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
—
20 + 0.1 CB
300
ns CB is specified to be
300
ns ^{from 10 to 400 pF}
1 MHz mode⁽²⁾
—
100
ns
IM21 TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
—
20 + 0.1 CB
1000
300
ns CB is specified to be
ns ^{from 10 to 400 pF}
1 MHz mode⁽²⁾
—
300
ns
IM25 TSU:DAT Data Input
100 kHz mode
250
—
ns
—
Setup Time
400 kHz mode
100
—
ns
1 MHz mode⁽²⁾
TBD
—
ns
IM26 THD:DAT Data Input
100 kHz mode
0
—
ns
—
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode⁽²⁾
TBD
—
ns
IM40 TAA:SCL Output Valid
100 kHz mode
—
3500
ns
—
From Clock
400 kHz mode
—
1000
ns
—
1 MHz mode⁽²⁾
—
—
ns
—
IM45
TBF:SDA
Bus Free Time
100 kHz mode
400 kHz mode
1 MHz mode⁽²⁾
4.7
1.3
TBD
—
s Time the bus must be
—
s ^{free before a new}
—
s ^{transmission can start}
IM50 CB
Bus Capacitive Loading
—
400
pF
—
Legend:
Note 1:
2:
TBD = To Be Determined
BRG is the value of the I²C Baud Rate Generator. Refer to Section 16.3 “Setting Baud Rate When
Operating as a Bus Master” for details.
Maximum pin capacitance = 10 pF for all I²C pins (for 1 MHz mode only).
 2010 Microchip Technology Inc.
DS39905E-page 297