PIC24FJ256GA110_10 Datasheet, PDF (294/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
FIGURE 28-14: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1)
SP60
SSx
SCKx
(CKP = 0)
SP50
SP52
SCKx
(CKP = 1)
SDOx
SP71
SP70
SP73
SP72
MSb
SP52
SP35
SP72
SP73
Bit 14 - - - - - -1
LSb
SDIx
SP30,SP31
MSb In
SP41
SP40
Bit 14 - - - -1
LSb In
SP51
TABLE 28-27: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Param
No.
Symbol
Characteristic
Min
Typ⁽¹⁾ Max Units Conditions
SP70 TscL
SCKx Input Low Time
30
—
—
ns
SP71 TscH
SCKx Input High Time
30
—
—
ns
SP72 TscF
SCKx Input Fall Time⁽²⁾
—
10
25
ns
SP73 TscR
SCKx Input Rise Time⁽²⁾
—
10
25
ns
SP30 TdoF
SDOx Data Output Fall Time⁽²⁾
—
10
25
ns
SP31 TdoR
SDOx Data Output Rise Time⁽²⁾
—
10
25
ns
SP35 TscH2doV, SDOx Data Output Valid after SCKx Edge
—
TscL2doV
—
30
ns
SP40 TdiV2scH, Setup Time of SDIx Data Input to
TdiV2scL SCKx Edge
20
—
—
ns
SP41 TscH2diL, Hold Time of SDIx Data Input to
TscL2diL SCKx Edge
20
—
—
ns
SP50 TssL2scH, SSx  to SCKx  or SCKx  Input
TssL2scL
120
—
—
ns
SP51 TssH2doZ SSx  to SDOx Output
High-Impedance⁽³⁾
10
—
50
ns
SP52 TscH2ssH SSx  after SCKx Edge
TscL2ssH
1.5 TCY + 40 —
—
ns
SP60 TssL2doV SDOx Data Output Valid after SSx Edge
—
—
50
ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
DS39905E-page 294
 2010 Microchip Technology Inc.