PIC24FJ256GA110_10 Datasheet, PDF (253/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
25.3.1 WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<6>) to ‘0’.
25.3.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
FIGURE 25-2:
SWDTEN
FWDTEN
LPRC Input
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
WDT BLOCK DIAGRAM
LPRC Control
FWPSA
31 kHz
Prescaler
(5-bit/7-bit)
WDT
Counter
1 ms/4 ms
WDTPS<3:0>
Postscaler
1:1 to 1:32.768
Wake from Sleep
WDT Overflow
Reset
25.4 Program Verification and
Code Protection
PIC24FJ256GA110 family devices provide two
complimentary methods to protect application code
from overwrites and erasures. These also help to
protect the device from inadvertent configuration
changes during run time.
25.4.1 GENERAL SEGMENT PROTECTION
For all devices in the PIC24FJ256GA110 family, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code
protection for this block is controlled by one Configura-
tion bit, GCP. This bit inhibits external reads and writes
to the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
 2010 Microchip Technology Inc.
DS39905E-page 253