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PIC24FJ256GA110_10 Datasheet, PDF (177/330 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select
PIC24FJ256GA110 FAMILY
To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register.
2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with the MSTEN bit
(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with the MSTEN bit
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 15-2:
SCKx
SSx/FSYNCx
SDOx
SDIx
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Sync
Control
Control
Clock
Select
Edge
Shift Control
bit0
SPIxSR
1:1 to 1:8
1:1/4/16/64
Secondary
Primary
FCY
Prescaler
Prescaler
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
Transfer
Transfer
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
Read SPIxBUF
SPIxBUF
Write SPIxBUF
16
Internal Data Bus
 2010 Microchip Technology Inc.
DS39905E-page 177