IS61NSCS25672 Datasheet, PDF (9/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
SPECIAL FUNCTIONS
Slow Down Mode
The SD pin allows the user to activate a delay element in
the on-chip clock chain that is routed to the data and echo
Clock output drivers. Activating Slow Down mode by
pulling the SD pin low introduces extra delay in every
synchronous output driver specification. Address, control
and data input specifications are not affected by Slow
Down Mode. See “Slow Down Mode Clock to Data Out and
Clock to Echo Clock Timing” table for specifics.
Burst Cycles
ΣRAMs provide an on-chip burst address generator that
can be utilized, if desired, to further simplify burst read or
write implementations. The ADV control pin, when driven
high, commands the ΣRAM to advance the internal ad-
dress counter and use the counter generated address to
read or write the ΣRAM. The starting address for the first
cycle in a burst cycle series is loaded into the ΣRAM by
driving the ADV pin low, into Load mode.
Burst Order
The burst address counter wraps around to its initial state
after four addresses (the loaded address and three more)
have been accessed. SigmaRAMs always count in linear
burst order.
Linear Burst Order
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
1. The burst counter wraps to initial state on the 5th rising edge
of clock.
Sigma Pipelined Burst Reads with Counter Wrap-around
CLK
External
Address
A2
XX
XX
XX
XX
XX
Internal
Address
A2
A3
A0
A1
A2
A3
Counter Wraps
E1
W
ADV
DQ
QA2
QA3
QA0
QA1
CQ
Read
Continue
Continue
Continue
Continue
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
ADVANCE INFORMATION Rev. 00A
06/19/01