IS61NSCS25672 Datasheet, PDF (24/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
JTAG PORT OPERATION
Overview
These devices provide a JTAG Test Access Port (TAP) and
Boundary Scan interface using a limited set of IEEE std.
1149.1 functions. This test mode is intended to provide a
mechanism for testing the interconnect between master
(processor, controller, etc.), SRAMs, other components,
and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these
devices contain a TAP Controller and four TAP Registers.
The TAP Registers consist of one Instruction Register
and three Data Registers (ID, Bypass, and Boundary
Scan Registers).
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG
port. The port is reset at power-up and will remain inactive
unless clocked. To assure normal operation of the RAM
with the JTAG Port unused, TCK should be tied Low, TDI
and TMS may be left floating or tied to VCC . TDO should
be left unconnected.
JTAG PIN DESCRIPTIONS
Pin
Pin Name I/O Description
TCK
Test Clock
In Clocks all TAP events. All inputs are captured on the rising edge of TCK and
all outputs propagate from the falling edge of TCK.
TMS
Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input
for the TAP controller. An undriven TMS input will produce the same result as
a logic one input level.
TDI
Test Data In
In The TDI input is sampled on the rising edge of TCK. This is the input side of the
serial registers placed between TDI and TDO. The register placed between TDI
and TDO is determined by the state of the TAP Controller and the instruction
that is currently loaded in the TAP Instruction Register (refer to the TAP
Controller State Diagram). An undriven TDI pin will produce the same result as
a logic one input level.
TDO
Test Data Out
Out Output that is active depending on the state of the TAP Controller. Output
changes in response to the falling edge of TCK. This is the output side of the
serial registers placed between TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while
TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01