IS61NSCS25672 Datasheet, PDF (10/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
Echo Clock
ΣRAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2
that track the performance of the output drivers. The Echo
Clocks are delayed copies of the main RAM clock, CLK.
Echo Clocks are designed to track changes in output
driver delays due to variance in die temperature and
supply voltage. The Echo Clocks are designed to fire with
the rest of the data output drivers. Sigma RAMs provide
both in-phase, or true, Echo Clock outputs (CQ1 and
CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and
E3 also deselects the Echo Clock output drivers. The
deselection of Echo Clock drivers is always pipelined to
the same degree as output data. Deselection of the RAM
via E1 does not deactivate the Echo Clocks.
In some applications it may be appropriate to pause
between banks; to deselect both RAMs with E1 before
resuming read operations. An E1 deselect at a bank
switch will allow at least one clock to be issued from the
new bank before the first read cycle in the bank. Although
the following drawing illustrates a E1 read pause upon
switching from Bank 1 to Bank 2, a write to Bank 2 would
have the same effect, causing the RAM in Bank 2 to issue
at least one clock before it is needed.
Echo Clock Control in Two Banks of Sigma Pipelined SRAMs
CLK
Address
A
B
C
D
E
F
E1
E2 Bank 1
E2 Bank 2
DQ Bank 1
QA
QC
DQ Bank 2
QB
QD
CQ Bank 1
CQ Bank 2
CQ1+ CQ2
Read
Read
Read
Read
Read
Read
Note:
E1 does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01