IS61NSCS25672 Datasheet, PDF (25/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
JTAG PORT REGISTERS
Overview
The JTAG registers, refered to as Test Access Port (TAP)
registers, are selected (one at a time) via the sequences
of 1s and 0s applied to TMS as TCK is strobed. Each of
the TAP registers are serial shift registers that capture
serial input data on the rising edge of TCK and push serial
data out on the next falling edge of TCK. When a register
is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are
executed by the TAP controller when it is moved into the
Run, Test/Idle, or the various data register states. In-
structions are 3 bits long. The Instruction Register can be
loaded when it is placed between the TDI and TDO pins.
The Instruction Register is automatically preloaded with
the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be
placed between TDI and TDO. It allows serial test data to
be passed through the RAM’s JTAG Port to another
device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be
preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be
shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan
Register also includes a number of place holder flip flops (always set
to a logic 1). The relationship between the device pins and the bits
in the Boundary Scan Register is described in the following Scan
Order Table. The Boundary Scan Register, under the control of the
TAP Controller, is loaded with the contents of the RAMs I/O ring
when the controller is in Capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to
Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST
instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
210
TDI
. . . ^{Instruction Register}
31 30 29
21 0
TDO
. . . . . ID Code Register
n
21 0
Boundary Scan Register
TMS
TCK
Test Access Port (TAP) Controller
Integrated Silicon Solution, Inc. — 1-800-379-4774
25
ADVANCE INFORMATION Rev. 00A
06/19/01