IS61NSCS25672 Datasheet, PDF (30/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
INSTRUCTION DESCRIPTIONS
BYPASS
When the BYPASS instruction is loaded to the Instruction
Register, the Bypass Register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
Shift-DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller
into the Capture-DR state loads the data in the RAMs input
and I/O buffers into the Boundary Scan Register. Some
Boundary Scan Register locations are not associated with
an input or I/O pin, and are loaded with the default state
identified in the BSDL file. Because the RAM clock is
independent from the TAP Clock (TCK) it is possible for
the TAP to attempt to capture the I/O ring contents while
the input buffers are in transition (i.e. in a metastable
state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results cannot
be expected. RAM input signals must be stabilized for
long enough to meet the TAP’s input data capture set-up
plus hold time (tTS plus tTH ). The RAM’s clock inputs need
not be paused for any other TAP operation except captur-
ing the I/O ring contents into the Boundary Scan Register.
Moving the controller to Shift-DR state then places the
Boundary Scan Register between the TDI and TDO pins.
EXTEST (EXTEST-A)
EXTEST is an IEEE 1149.1 mandatory public instruction.
It is to be executed whenever the instruction register is
loaded with all logic 0s. The EXTEST command does not
block or override the RAM’s input pins; therefore, the
RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the
desired pattern of data with the SAMPLE/PRELOAD
command. Then the EXTEST command is used to output
the Boundary Scan Register’s contents, in parallel, on the
RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in
parallel using the EXTEST command. When the EXTEST
instruction is selected, the state of all the RAM’s input and
I/O pins, as well as the default values at Scan Register
locations not associated with a pin (pin marked NC), are
transferred in parallel into the Boundary Scan Register on
the rising edge of TCK in the Capture-DR state, the RAM’s
output pins drive out the value of the Boundary Scan
Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
to the ID register when the controller is in Capture-DR
mode and places the ID register between the TDI and TDO
pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in at power up and any time the
controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded to the instruction
register, all RAM outputs are forced to inactive state
(high-Z) and the Boundary Scan Register is connected
between TDI and TDO when the TAP controller is moved
to the Shift-DR state.
RFU
These instructions are reserved for future use. In this
device they replicate the BYPASS instruction.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01