IS61NSCS25672 Datasheet, PDF (26/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
a 32-bit on-chip ROM. It describes various attributes of
the RAM as indicated below. The register is then placed
between the TDI and TDO pins when the controller is
moved into Shift-DR state. Bit 0 in the register is the LSB
and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
ISSI Technology
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1
JTAG TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test Idle ¹
0
Select DR ¹
0
1 _{Capture DR}
0
Shift DR
10
1 _{Exit1 DR}
0
Pause DR
10
Exit2 DR ₀
1
1 _{Update DR}
0
Select IR ¹
0
1 _{Capture IR}
0
Shift IR
10
1 _{Exit1 IR}
0
Pause IR
10
Exit2 IR ₀
1
1 _{Update IR}
0
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01