IS61NSCS25672 Datasheet, PDF (13/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
Programmable Enables
SRAMs feature two user-programmable chip enable inputs,
E2 and E3. The sense of the inputs, whether they function
as active low or active high inputs, is determined by the
state of the programming inputs, EP2 and EP3. For
example, if EP2 is held at VCC , E2 functions as an active
high enable. If EP2 is held to GND , E2 functions as an
active low chip enable input.
Programmability of E2 and E3 allows four banks of depth
expansion to be accomplished with no additional logic. By
programming the enable inputs of four SRAMs in binary
sequence (00, 01, 10, 11) and driving the enable inputs
with two address inputs, four SRAMs can be made to look
like one larger RAM to the system.
BANK ENABLE TRUTH TABLE
Bank 0
Bank 1
Bank 2
Bank 3
EP2
GND
GND
Vcc
Vcc
EP3
GND
Vcc
GND
Vcc
E2
Active Low
Active Low
Active High
Active High
E3
Active Low
Active High
Active Low
Active High
EXAMPLE FOUR BANK DEPTH EXPANSION SCHEMATIC
A0-An
E1
CLK
W
DQ0-DQn
CQ
Bank 0
A0-An-2
An-1
A
E3
An
E2
E1
CLK
W
DQ
CQ
Bank 1
A0-An-2
An-1
A
E3
An
E2
E1
CLK
W
DQ
CQ
Bank 2
A0-An-2
An-1
A
E3
An
E2
E1
CLK
W
DQ
CQ
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
Bank 3
A0-An-2
An-1
A
E3
An
E2
E1
CLK
W
DQ
CQ
13