IS61NSCS25672 Datasheet, PDF (14/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
SYNCHRONOUS TRUTH TABLE
CLK E1 E ADV W BW
(tn) (tn) (tn) (tn) (tn)
Previous
Operation
Current Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
0→1 X F 0 X X
X
Bank Deselect
***
Hi-Z
0→1 X X 1 X X
Bank Deselect
Bank Deselect (Continue)
Hi-Z
Hi-Z
0→1 1 T 0 X X
X
Deselect
***
Hi-Z/CQ
0→1 X X 1 X X
Deselect
Deselect (Continue)
Hi-Z/CQ Hi-Z/CQ
0→1 0 T 0 0 T
X
Write
Loads new address
Stores DQx if BWx = 0
***
Dn/CQ
(tn)
0→1 0 T 0 0 F
X
Write (Abort)
Loads new address
No data stored
***
Hi-Z/CQ
0→1 X X 1 X T
Write
Write Continue
Increments address by 1
Stores DQx if BWx = 0
Dn-1/CQ Dn/CQ
(tn-1)
(tn)
0→1 X X 1 X F
Write
Write Continue (Abort)
Increments address by 1
No data stored
Dn-1/CQ Hi-Z/CQ
(tn-1)
0→1 0 T 0 1 X
X
Read
Loads new address
***
Qn/CQ
(tn)
0→1 X X 1 X X
Read
Read Continue
Increments address by 1
Qn-1/CQ Qn/CQ
(tn-1)
(tn)
Notes:
1. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
2. If one or more BWx = 0 then BW = “T” else BW = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
5. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to 3 Continue operations may be initiated after iniating a Read or Write operation to burst transfer up to 4 distinct pieces of data per single
external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01