IS61NSCS25672 Datasheet, PDF (2/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ISSI ^®
Functional Description
Because SigmaRAM is a synchronous device, address,
data Inputs, and read/write control inputs are captured on
the rising edge of the input clock. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation required by asynchronous SRAMs and
simplifies input signal timing.
Single data rate ΣRAMs incorporate a rising-edge-triggered
output register. For read cycles, ΣRAM’s output data is
temporarily stored by the edge-triggered output register
during the access cycle and then released to the output
drivers at the next rising edge of clock.
IS61NSCS series ΣRAMs are implemented with ISSI’s
high performance CMOS technology and are packaged in
a 209-bump BGA.
IS61NSCS25672 PINOUT
256K x 72 Common I/O—Top View
1
2
3
4
5
6
A DQg
DQg
A
B DQg
DQg
Bc
E2
A
ADV
(16M)
Bg
NC
W
C DQg
DQg
Bh
D DQg
E DQPg
F DQc
G DQc
H DQc
J DQc
K CQ2
L DQh
M DQh
N DQh
P DQh
R DQPd
T DQd
U DQd
DQg
DQPc
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
GND
VCCQ
GND
VCCQ
GND
VCCQ
CLK
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
V DQd
DQd
A
W DQd
DQd
TMS
Bd
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDI
NC
(128M)
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(64M)
A
A
E1
MCL
VCC
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
VCC
MCL
A
A1
A0
11 x 19 Bump BGA—14 x 22 mm² Body—1 mm Bump Pitch
7
A
(8M)
A
NC
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(32M)
A
A
8
E3
Bb
Be
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDO
9
10
11
A
DQb
DQb
Bf
DQb
DQb
Ba
DQb
DQb
GND
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
DQb
DQPf
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQb
DQPb
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
A
DQe
DQe
TCK
DQe
DQe
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01