IS61NSCS25672 Datasheet, PDF (23/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
TIMING PARAMETER KEY—PIPELINED READ CYCLE TIMING
CK
tAVKH
tKHAX
C
DQ (DDR)
tKHQV
tKHQX1
tKHCH
tKHCX1
tCHQV
tCHCL
tKHKH
tKHKL
tKLKH
D
E
tKHQZ
tKHQX
QB
tCHQX
tCLCH
tKHCZ
CQ
= CQ High Z
ISSI ^®
TIMING PARAMETER KEY—DOUBLE LATE WRITE MODE CONTROL AND DATA IN TIMING
CK
tAVKH
A
A
tKHAX
E1, E2, E3
W, Bn, ADV
B
tnVKH
tKHnX
DQ
C
tDVKH
DA
tKHDX
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
23
ADVANCE INFORMATION Rev. 00A
06/19/01