IS61NSCS25672 Datasheet, PDF (15/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
READ/WRITE CONTROL STATE DIAGRAM
ISSI ^®
0,T,0,1
READ
0,T,0,0
X,F,0,X
0,T,0,1
0,T,0,0
WRITE
X,X,1,X
0,T,0,0 ^0,T,0,1
X,X,1,X
READ
CONTINUE
1,T,0,X
0,T,0,1
X,F,0,X or
X,X,1,X
X,F,0,X
0,T,0,1
1,T,0,X
0,T,0,0
BANK
DESELECT
X,F,0,X
X,X,1,X
1,T,0,X
0,T,0,1
X,F,0,X
0,T,0,0
X,F,0,X
X,X,1,X
1,T,0,X
WRITE
CONTINUE
1,T,0,X
1,T,0,X or
X,X,1,X
DESELECT
0,T,0,0
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
ADVANCE INFORMATION Rev. 00A
06/19/01