IS61NSCS25672 Datasheet, PDF (1/32 Pages) Integrated Silicon Solution, Inc – RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

IS61NSCS25672
IS61NSCS51236
ΣRAM 256K x 72, 512K x 36
18Mb Synchronous SRAM
ISSI^®
ADVANCE INFORMATION
JUNE 2001
Features
• JEDEC SigmaRam pinout and package standard
• Single 1.8V power supply (VCC): 1.7V (min)
to 1.9V (max)
• Dedicated output supply voltage (VCCQ): 1.8V
or 1.5V typical
• LVCMOS-compatible I/O interface
• Common data I/O pins (DQs)
• Single Data Rate (SDR) data transfers
• Pipelined (PL) read operations
• Double Late Write (DLW) write operations
• Burst and non-burst read and write operations,
selectable via dedicated control pin (ADV)
• Internally controlled Linear Burst address
sequencing during burst operations
• Burst length of 2, 3, or 4, with automatic address
wrap
• Full read/write coherency
• Byte write capability
• Two cycle deselect
• Single-ended input clock (CLK)
• Data-referenced output clocks (CQ/CQ)
• Selectable output driver impedance via dedicated
control pin (ZQ)
• Echo clock outputs track data output drivers
• Depth expansion capability (2 or 4 banks) via
programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard
1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball
Grid Array (BGA) package
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
SigmaRAM Family Overview
The IS61NSCS series ΣRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
The implementations are 18,874,368-bit (18Mb) SRAMs.
These are the first in a family of wide, very low voltage CMOS
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking
systems.
ISSI’s ΣRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs.
The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of
address bursting, output data registering and write cueing.
ΣRAMs allow a user to implement the interface protocol best
suited to the task at hand.
This specific product is Common I/O, SDR, Double Late
Write & Pipelined Read (same as Pipelined NBT) and in
the family is identified as 1x1Dp.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
ADVANCE INFORMATION Rev. 00A
06/19/01