TC1130 Datasheet, PDF (98/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Timing for Multiplexed Access Signals
(Operating Conditions apply; C_L = 50 pF)¹⁾
Parameter
Symbol
Limits
Unit
min max
ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid t₁ CC −
time from output clock
3.2 ns
ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold t₂ CC 0.0 −
ns
time from output clock
AD(31:0) output valid time from output clock
AD(31:0) output hold time from output clock
AD(31:0) input setup time to output clock
AD(31:0) input hold time from output clock
WAIT input setup time to output clock
WAIT input hold time from output clock
RMW output valid time from output clock
RMW output hold time from output clock
ADV width
AD(31:0) output hold time from RD/WR
t₃ CC −
2.6 ns
t₄ CC 0.0 −
ns
t₅ SR 1.4 −
ns
t₆ SR 0.8 −
ns
t₉ SR 10.6 −
ns
t₁₀ SR 0.0
−
ns
t₁₁ CC −
6.3 ns
t₁₂ CC 1.3
−
ns
t₁₃ CC 10.0 −
ns
t₁₄ CC 0
−
ns
1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to
user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals
with correct timing sequence. It is user’s responsibility to program the correct phase length according to the
memory/peripheral device specification and EBU Specification.
Data Sheet
94
V0.3, 2003-09