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TC1130 Datasheet, PDF (104/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller
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TC1130
SSC Master Mode Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
min.
max.
SCLK clock frequency
1 / t SCLK CC -
25
SCLK clock high time
t1
CC 18
-
SCLK clock low time
t2
CC 18
-
SCLK clock rise time
t3
CC -
11
SCLK clock fall time
t4
CC -
11
MTSR/SLSOx low/high from SCLK t 5
CC -
2.0
edge
MRST setup to SCLK edge
t6
SR 7
-
MRST hold from SCLK edge
t7
SR 5
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
SCLK
(CON.PO,CON.PH = 00 or 11)
tSCLK
t1
t
2
t4
t3
0.9 VDD
0.1 VDD
SCLK
(CON.PO,CON.PH = 01 or 10)
t2
t1
t5
t
t
3
4
0.9 V
DD
0.1 VDD
MTSR
SLSOx1)
State n-1
t5
State n
State n+1
MRST
t6
t7
Data valid
Data valid
Figure 34
1) The transition SLSOxis based on the following setup:
SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of
a transmission.
SSC Master Mode Timing
Data Sheet
100
V0.3, 2003-09
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