TC1130 Datasheet, PDF (54/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
On-Chip Bus System
The TC1130 includes two bus systems:
– Local Memory Bus (LMB)
– On-Chip FPI Bus (FPI)
The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus.
Local Memory Bus (LMB)
The Local Memory Bus interconnects the memory units and functional units, such as
CPU and DMU. The main target of the LMB bus is to support devices with fast response
times, optimized for speed. This allows the DMI and PMI fast access to local memory
and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via
External Bus Unit, it interconnects TC1130 and external components.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8, 16, 32 & 64 bits single beat transactions and variable
length 64 bits block transfers.
Key Features
The LMB provides the following features:
• Synchronous, Pipelined, Multi-master, 64-bit high performance bus
• Optimized for high speed and high performance
• 32 bit address, 64 bit data busses
• Support Split transactions
• Support Variable block size transfer
• Burst Mode Read/Write to Memories
• Connect Caches and on-chip memory and FPI Bus
• Slave controlled wait state insertion
• Support Locked transaction (read-modify-write)
Data Sheet
50
V0.3, 2003-09