TC1130 Datasheet, PDF (59/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
The basic structure and external interconnections of the DMA are shown in Figure 15
Clock
Control
f _DMA
DMA Controller
Address
Decoder
Arbiter/
Switch Control
4
MultiCAN
2
ASC0
2
ASC1
2
ASC2
2
8
SSC0
2
SSC1
1
CCU60
1
CCU61
4
MLI0
4
MLI1
DMA
Request
Wiring
Matrix
8
1
I2C
1
USB
SCU
4
4
(Ext.Trg)
Interrupt
Control
SR [3:0]
SR [15:12]
DMA Sub-Block 0
Request
Assignment
and
Priorisation
Unit 0
Channel
00-07
Registers
Transaction
Control Engine
DMA Interrupt Control Unit
Bus
Interface 0
M/S
Bus
Interface 1
M/S
Bus
Interface 2
SMIF
Figure 15 DMA Controller Structure and Interconnections
To FPI Bus
ASC0
ASC1
ASC2
SSC0
SSC1
IIC
MLI0
MLI1
Mem Check
TC1130_DMAImplementation
Data Sheet
55
V0.3, 2003-09