TC1130 Datasheet, PDF (92/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Timing for SDRAM Access Signals
(Operating Conditions apply; C_L = 50 pF¹⁾)
Parameter
Symbol
Limits
Unit
min max
CKE output valid time from SDCLKO
t₁ CC −
8.0 ns
CKE output hold time from SDCLKO
t₂ CC 1.0 −
ns
Address output valid time from SDCLKO
t₃ CC −
8.0 ns
Address output hold time from SDCLKO
t₄ CC 1.0 −
ns
CSx, RAS, CAS, RD/WR, BC(3:0) output valid time t₅ CC −
from SDCLKO
8.0 ns
CSx, RAS, CAS, RD/WR, BC(3:0) output hold time t₆ CC 1.0 −
ns
from SDCLKO
AD(31:0) output valid time from SDCLKO
AD(31:0) output hold time from SDCLKO
AD(31:0) input setup time to SDCLKO
AD(31:0) input hold time from SDCLKO
t₇ CC −
8.0 ns
t₈ CC 1.0 −
ns
t₉ SR 4.0 −
ns
t₁₀ SR 3.0 −
ns
1) If application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be
used for your specific application condition. For design team, the load should be set according to the system
requirement.
Data Sheet
88
V0.3, 2003-09