TC1130 Datasheet, PDF (19/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Table 1
Pin Definitions and Functions(cont’d)
Symbol Pin
TRST
T11
TCK
T12
TDI
T13
TDO
T10
TMS
T9
TRCLK T8
HWCFG0 M14
HWCFG1 L14
HWCFG2 T6
BRKIN T5
MII_
T2
TXCLK
MII_
R2
RXCLK
MII_
R1
MDIO
D+
T14
D-
T15
In PU/ Functions
Out PD¹⁾
I PDC JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
I PUC JTAG Module Clock Input
I PUC JTAG Module Serial Data Input
O  JTAG Module Serial Data Output
I PUC JTAG Module State Machine Control Input
O  Trace Clock for OCDS_L2 Lines
I PUC Hardware Configuration Inputs
I PUC The Configuration Inputs define the boot options of the
I PDC TC1130 after a hardware invoked reset operation.
I PUC OCDS Break Input
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
I PDC Ethernet Controller Transmit Clock
MII_TXD[3:0] and MII_TXEN are driven off the rising
edge of the MII_TXCLK by the core and sampled by
the PHY on the rising edge of the MII_TXCLK.
I PDC Ethernet Controller Receive Clock
MII_RXCLK is a continuous clock. Its frequency is 25
MHz for 100 Mbps operation, and 2.5 MHz for 10Mbps.
MII_RXD[3:0], MII_RXDV and MII_EXER are driven
by the PHY off the falling edge of MII_RXCLK and
sampled on the rising edge of MII_RXCLK.
I/O PDA Ethernet Controller Management Data Input /
Output
When a read command is being executed, data which
is clocked out of the PHY will be presented on the input
line. When the Core is clocking control or data onto the
MII_MDIO line, the signal will carry the information.
I/O  USB D+ data line
I/O  USB D- data line
Data Sheet
15
V0.3, 2003-09