TC1130 Datasheet, PDF (68/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
On-Chip Debug Support
The On-Chip Debug Support of the TC1130 consists of the following building blocks:
• OCDS L1 module of TriCore
• OCDS L2 interface of TriCore
• OCDS L1 module in the BCU of the FPI Bus
• OCDS L1 facilities within the DMA
• OCDS L2 interface of DMA
• OCDS System Control Unit (OSCU)
• Multi Core Break Switch (MCBS)
• JTAG based Debug Interface (Cerberus JDI)
• Suspend functionality of peripherals
Features
• TriCore L1 OCDS:
– Hardware event generation unit
– Break by DEBUG instruction or break signal
– Full Single-Step support in hardware, possible also with software break
– Access to memory, SFRs, etc. on the fly
• DMA L1 OCDS:
– Output break request on errors
– Suspending of pre-selected channels
• Level 2 trace port with 16 pins that outputs either TriCore, or DMA trace
• OCDS System Control Unit (Cerberus OSCU)
– Minimum number of pins required (no OCDS enable pin)
– Hardware allows hot attach of a debugger to a running system
– System is secure (can be locked from internal)
• Multi Core Break Switch (Cerberus MCBS):
– TriCore, DMA, break pins, and BCUs as break sources
– TriCore as break targets; other parts can in addition be suspended
– Synchronous stop and restart of the system
– Break to Suspend converter
Figure 18 shows a basic block diagram of the building blocks.
Data Sheet
64
V0.3, 2003-09