TC1130 Datasheet, PDF (55/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
On-Chip FPI Bus
The FPI Bus interconnects the functional units of the TC1130, such as the DMA and on-
chip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip
functional units, and quick to transfer data. The low setup overhead of the FPI Bus
access protocol guarantees fast FPI Bus acquisition, which is required for time-critical
applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak
transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32-
bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate
at close to its peak bandwidth.
Features
• Supports multiple bus masters
• Supports demultiplexed address/data operation
• Address bus up to 32 bits and data buses are 64 bits wide
• Data transfer types include 8-, 16-, 32- and 64 bit sizes
• Supports Burst transfer
• Single- and multiple-data transfers per bus acquisition cycle
• Designed to minimize EMI and power consumption
• Controlled by an Bus Control Unit (BCU)
– Arbitration of FPI Bus master requests
– Handling of bus error.
LFI
The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI
bus to the Local Memory Bus (LMB).
LFI Features
• Compatible with the FPI 3.2 and LMB bus Specification V2.4
• Supports Burst/Single transactions, from FPI to LMB.
• Supports Burst/Single transactions, from LMB to FPI
• High efficiency and performance:
– fastest access across the bridge takes three cycles, using a bypass.
– There are no dead cycles on arbitration.
• Acts as the default master on FPI side.
• Supports abort, error and retry conditions on both sides of the bridge.
• Supports FPI’s clock the same, or half, as the LMB’s clock frequency.
• LMB clock is shut when no transactions are issue to LFI from both buses and none
are in process in the LFI to minimize the power consumption.
Data Sheet
51
V0.3, 2003-09