TC1130 Datasheet, PDF (85/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
V _DDPPA
VDDP
V _DDPPA
VDD
t_{o s c s}
V _DDPR
OSC
PORST
HDRST
Pads
Pad-
state
undefined
t_{PO A}
t_{P O A}
t_{h d}
t_{h d}
2)
1)
2)
t_pi
1) as program m ed
2) Tri-state, pull device active
1)
2)
Pad-
state
undefined
reset_beh
PLL Parameters
Phase Locked Loop (PLL)
When PLL operation is configured (PLL_CLC.LOCK = 1) the on-chip phase locked loop
is enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (f_MC = f_OSC × F) which results from the input divider, the multiplication factor (N
Factor), and the output divider (F = NDIV+1 / (PDIV+1 × KDIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f_MC is constantly adjusted so it
is locked to f_OSC. The slight variation causes a jitter of f_MC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because f_CPU is derived from
f_MC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 23).
Data Sheet
81
V0.3, 2003-09