TC1130 Datasheet, PDF (52/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Table 3
Block Address Map of Segment 15(cont’d)
Symbol Description
Address Range
Size
DMU
-
DMI
PMI
LBCU
LFI
–
Data Memory Unit
Reserved
Data Memory Interface Unit
Program Memory Interface Unit
Local Memory Bus Control Unit
LMB to FPI Bus Bridge
Reserved
F800 0400_H - F800 04FF_H 256 Bytes
F800 0500_H -F87F FBFF_H –
F87F FC00_H-F87FFCFF_H 256 Bytes
F87F FD00_H-F87FFDFF_H 256 Bytes
F87F FE00_H - F87F FEFF_H 256 Bytes
F87F FF00_H - F87F FFFF_H 256 Bytes
F880 0000_H - FFFF FFFF_H –
Memory Protection System
The TC1130 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the kinds of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
In TC1130, TriCore supports two address spaces: The virtual address space and The
physical address space. Both address space are 4GB in size and divided into 16
segments with each segment being 256MB. The upper 4 bits of the 32-bit address are
used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address
is always translated into a physical address before accessing memory. The virtual
address is translated into a physical address using one of two translation mechanisms:
(a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual
address belongs to the upper half of the virtual address space then the virtual address is
directly used as the physical address (direct translation). If the virtual address belongs to
the lower half of the address space, then the virtual address is used directly as the
physical address if the processor is operating in Physical mode (direct translation) or
translated using a Page Table Entry if the processor is operating in Virtual mode (PTE
translation). These are managed by Memory Management Unit (MMU)
Memory protection is enforced using separate mechanisms for the two translation paths.
Protection for direct translation
Memory protection for addresses that undergo direct translation is enforced using the
range based protection that has been used in the previous generation of the TriCore
architecture. The range based protection mechanism provides support for protecting
Data Sheet
48
V0.3, 2003-09