TC1130 Datasheet, PDF (86/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = KDIV+1) to generate the master clock signal f_MC. Therefore, the
number of VCO cycles can be represented as K × N, where N is the number of
consecutive f_MC cycles (TCM).
For a period of N × TCM the accumulated PLL jitter is defined by the corresponding
deviation D_N:
D_N [ns] = ±(1.5 + 6.32 × N / f_MC); f_MC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D₃ = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K×N=95 value can be
used. This steady value can be approximated by: D_Nmax [ns] = ±(1.5 + 600 / (K × f_MC)).
Acc. jitter D _N
ns
±8
K=15 K=12 K=10 K=8
±7
±6
±5
±4
±3
2400MMHzHz
±2
±1
K=6
K=5
01
5
10
15
20
25
N
m cb 04413_x c.vsd
Figure 23 Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Data Sheet
82
V0.3, 2003-09