TC1130 Datasheet, PDF (18/113 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Table 1
Symbol
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
HDRST
PORST
NMI
Pin Definitions and Functions(cont’d)
Pin In PU/ Functions
Out PD¹⁾
I/O
Port 4
Port 4 is a 8-bit bidirectional general purpose I/O port
which can be alternatively used for USB, MLI0 and
SCU.
R8 I PUC USBCLK
48MHz input clock
O
TCLK0B
MLI0 transmit channel clock output B
R9 I PUC RCVI
USB data input
I
TREADY0B MLI0 transmit channel ready input B
N7 I PUC VPI
USB D+ CMOS level mirror of differential
signal
O
TVALID0B MLI0 transmit channel valid output B
N6 I PUC VMI
USB D- CMOS level mirror of differential
signal
O
TDATA0B MLI0 transmit channel data output B
P6 O PUC VPO
USB D+ CMOS level output
I
RCLK0B
MLI0 receive channel clock input B
R7 O PUC VMO
USB D- CMOS level output
O
RREADY0B MLI0 receive channel ready output B
R6 O PUC USBOE
Direction select for transmit or receive
I
RVALID0B MLI0 receive channel valid input B
P5 I PUC RDATA0B MLI0 receive channel data input B
O
BRKOUT#_A OCDS Break Out A
N5 I/O PUA Hardware Reset Input/Reset Indication Output
Assertion of this bidirectional open-drain pin causes a
synchronous reset of the chip through external
circuitry. This pin must be driven for a minimum
duration.
The internal reset circuitry drives this pin in response
to a power-on, hardware, watchdog and power-down
wake-up reset for a specific period of time. For a
software reset, activation of this pin is programmable.
R5 I PUC Power-on Reset Input
A low level on PORST causes an asynchronous reset
of the entire chip. PORST is a fully asynchronous level
sensitive signal.
T7 I PUC Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
Data Sheet
14
V0.3, 2003-09