TC1796 Datasheet, PDF (74/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Functional Description
3.22
On-Chip Debug Support
Figure 18 shows a block diagram of the TC1796 OCDS system.
TriCore
CPU
SBCU
RBCU
TR[15:0]
TRCLK
TDI
TDO
TMS
TCK
TRST
BRKIN
BRKOUT
PCP2
M
U
X
Cerberus
OCDS
System
Control Unit
(OSCU)
JTAG
Controller
JTAG
Debug
Interface
(JDI)
Multi Core
Break
Switch
(MCBS)
Watchdog
Timer
(WDT )
DMA
Controller
(Bus Bridge)
System
Peripheral
Bus
SPB
Peripheral
Unit 1
SPB
Peripheral
Unit m
RPB
Peripheral
Unit 1
RPB
Peripheral
Unit n
MCB05756_mod
Figure 18 OCDS System Block Diagram
The TC1796 basically supports three levels of debug operation:
• OCDS Level 1 debug support
• OCDS Level 2 debug support
• OCDS Level 3 debug support
Data Sheet
74
V1.0, 2008-04